By Peter Stallhofer (auth.), Joachim Burghartz (eds.)
Ultra-thin Chip expertise and purposes edited via: Joachim N. Burghartz Ultra-thin chip know-how has the aptitude to supply recommendations for overcoming bottlenecks in silicon know-how and for resulting in new functions. This ebook exhibits how very skinny and versatile chips will be fabricated and utilized in many new functions in microelectronics, microsystems, biomedical and different fields. It offers a accomplished connection with the fabrication expertise, submit processing, meeting, characterization, modeling and functions of ultra-thin chips. •Provides a accomplished evaluate of the demanding situations in ultra-thin chip fabrication, put up processing, houses and functions via leaders within the box sharing their most modern effects and ideas; •Compares strengths and weaknesses of 3 primary fabrication procedures for ultra-thin chips; •Describes digital, mechanical, optical, and thermal houses of ultra-thin chips which are assorted from these of traditional, thick chips; •Shows that skinny chip expertise and its purposes represents a brand new paradigm in silicon technology.
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Additional resources for Ultra-thin Chip Technology and Applications
In the case of wafers of standard thickness micro defects are generally not an C. N. 1007/978-1-4419-7276-7_4, # Springer Science+Business Media, LLC 2011 33 34 C. Landesberger et al. issue, because the rigid silicon substrate prevents the propagation of flaws towards the transistor regions. For ultra-thin wafers such a ‘safety belt’ against breakage no longer exists. Micro cracks from any side of a semiconductor chip will run through the crystal lattice as soon as the substrate is strongly bent.
These applications benefit strongly from Moore’s law and are currently in the sub 100-nm regime. CMOS technology provides the platform for making the smallest possible feature size for electronic devices such as microprocessors, memory and logic circuits. Approximately 70–80% of silicon wafers are used in feature size critical CMOS applications. They are almost exclusively manufactured on 200-mm and 300-mm diameter wafers. 4 More than Moore Applications In addition to the wafers used in CMOS-based applications a further 20% of silicon wafers are used for discrete (as opposed to integrated) devices, which find applications in power electronic sensors and micro-electro-mechanical systems (MEMS).
Subsequently, backside thinning is performed until the frontside grooves are opened. Then separated thin dies will be transferred onto a tape, which allows for a pick-and-place process for final assembly. This basic concept allows for a variety of adaptations and variations. First, the frontside trenches may be prepared by half-cut sawing, wet etching or plasma etching. Reversible bonding of a rigid support substrate can be realised by releasable tapes, solvable glues or thermoplastic materials.
Ultra-thin Chip Technology and Applications by Peter Stallhofer (auth.), Joachim Burghartz (eds.)